A buried contact is an electrical contact that connects polysilicon layer to a doped region in a semiconductor substrate. Buried contacts have been widely used in CMOS SRAM circuit. A CMOS SRAM cell contains two load resistors, two pull down transistors and two pass transistors. One of the pull down transistors utilizes buried contact to connect gate electrode to the drain of the other pull down transistor. In a typical CMOS SRAM cell layout, the drains of the pull down transistors also serve as the drains of the pass transistors that provide access from the bit lines to the memory cells.
A typical process for the formation of a buried contact by a prior art method is shown in FIGS. 1a through 1e. Shown in FIG. 1a, is a P- type semiconductor substrate 12 that has undergone some of the processing steps in the fabrication of a semiconductor device. A thin oxide layer 14 is formed onto the surface of substrate 12 and functions as a gate dielectric layer. A thin polysilicon layer 16 is immediately deposited after the thin oxide layer 14 is formed. The thin polysilicon layer 16 and the thin oxide layer 14 are patterned using photo resist mask 18 (FIG. 1b) and etched to form a buried contact 20 (FIG. 1c). Photo resist mask is then removed and a thick polysilicon layer 24 is deposited on the thin polysilicon layer 16 and the buried contact region 20. Subsequentlys the substrate 12 is doped with phosphorous oxychloride (POCl.sub.3) to reduce the resistance of the polysilicon layers 16 and 24, and to form an N+ region 22 in the substrate 12 as shown in FIG. 1d. The polysilicon layers 16 and 24 are patterned by a photo resistor mask and etched by an anisotropic etch process to form a transistor gate electrode 27 and interconnect 26. This is shown in FIG. 1e. The anisotropic etch process also etches the silicon substrate 12 at about the same etch rate, since both the polysilicon and the silicon substrate contain silicon. A trench 30 is formed during the etching process used to form the gate electrode 27 and the interconnect 26. The formation of trench 30 is undesirable because it provides a leakage path between the N+ region 22 and the substrate 12.
It is therefore an object of the present invention to provide a method of forming buried contacts in a semiconductor substrate that does not have the drawbacks and the shortcomings of the prior art methods.
It is another object of the present invention to provide a method of forming damage-free buried contacts in a semiconductor substrate.
It is a further object of the present invention to provide a method of forming buried contacts in a semiconductor substrate that does not produce defects such as trenches or pitted areas.
It is still another object of the present invention to provide a method of forming buried contacts in a semiconductor substrate that does not produce trenches and the subsequent leakage paths between the N+ region and the P- type silicon substrate.
It is another further object of the present invention to provide a method of forming buried contacts in a semiconductor substrate that utilizes etching gases having high etching selectivity between different materials in the substrate.
It is yet another object of the present invention to provide a method of forming buried contacts in a semiconductor substrate that utilizes etching gases that have high etching selectivity between different materials of polysilicon, silicon oxide and single crystalline silicon.